1. Field of the Invention
The invention relates a gate signal line drive circuit and a display using the same. In particular, the invention relates to suppression of a leak current in a gate signal line drive circuit.
2. Description of the Related Art
Up to now, for example, in a liquid crystal display device, a circuit thin film transistors (hereinafter referred to as “TFT”) arranged in pixel areas of a display screen are formed on the same substrate, that is, a circuit with a built-in shift register may be employed.
The shift register circuit provided in the gate signal line drive circuit outputs agate signal Gout, which becomes a high voltage in a signal high period, and becomes a low voltage in a signal low period which is a period other than the signal high period, to a corresponding gate signal line.
FIG. 17 is a schematic diagram illustrating a configuration of a shift register circuit in a related art. The shift register circuit includes a high voltage supply switching element SWG that supplies a high voltage to the gate signal line in response to the signal high period, a low voltage supply switching element SWA that supplies a low voltage to the gate signal line in response to the signal low period, and a high voltage supply off control element SWB that supplies a low voltage to a switch (control terminal) of the high voltage supply switching element SWG in response to the signal low period.
A low voltage line VGL is connected to an input terminal of the low voltage supply switching element SWA. In response to the signal low period, the low voltage supply switching element SWA turns on and the low voltage supply switching element SWA outputs the low voltage which is a voltage of the low voltage line VGL. The low voltage supply switching element SWA turns off in response to the signal high period. The high voltage is supplied to a switch (control terminal) of the low voltage supply switching element SWA while the low voltage supply switching element SWA is on.
A basic clock signal CLK which becomes high voltage in the signal high period is connected to an input terminal of the high voltage supply switching element SWG. The high voltage supply switching element SWG turns on in response to the signal high period, and the high voltage supply switching element SWG outputs a voltage of the basic clock signal CLK, and the high voltage supply switching element SWG turns off in response to the signal low period. The high voltage is supplied to the switch of the high voltage supply switching element SWG while the high voltage supply switching element SWG is on, and the low voltage is supplied to the switch of the high voltage supply switching element SWG while the high voltage supply switching element SWG is off.
A high voltage supply off control element SWB that supplies the low voltage in response to the signal low period is connected to the switch of the high voltage supply switching element SWG. The low voltage line VGL is connected to an input terminal of the high voltage supply off control element SWB. The high voltage supply off control element SWB turns on in response to the signal low period, and the high voltage supply off control element SWB supplies the low voltage to the switch of the high voltage supply switching element SWG. The high voltage supply off control element SWB turns off in response to the signal high period. The high voltage is supplied to the switch (control terminal) of the high voltage supply off control element SWB while the high voltage supply off control element SWB is on.
Most of one frame period for displaying one screen is the signal low period. Hence, the high voltage is supplied to the respective switches of the low voltage supply switching element SWA and the high voltage supply off control element SWB in response to the signal low period for a long period. The low voltage supply switching element SWA and the high voltage supply off control element SWB become on for a long period, and those elements are deteriorated earlier than the other elements. A gate signal line drive circuit in which a plurality of elements are arranged in parallel in order to suppress the deterioration of those elements, and at least any one of the plurality of elements is driven under the control, to thereby suppress the deterioration of the elements is disclosed in JP 2010-256422 A.